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8023A 8023A MCC Manchester Code Converter
TM
92123
Features
s Compatible with IEEE 802.3 /Ethernet (10BASE5), IEEE802.3/CHEAPERNET (10BASE2) and Ethernet Rev. 1 Specifications s Compatible with 8003 ELDC (R), 8005 Advanced EDLC and Intel 82586 LAN Controller s Manchester Data Encoding/Decoding and Receiver Clock Recovery with Phase Locked Loop (PLL) s Receiver and Collision Squelch Circuit and Noise Rejection Filter s Differential TRANSMIT Cable Driver s Loopback Capability for Diagnostics and Isolation s Fail-Safe Watchdog Timer Circuit to Prevent Continuous Transmission s 20 MHz Crystal Oscillator s Transceiver Interface High Voltage (16 V) Short Circuit Protection s Low Power CMOS Technology with Single 5V Supply s 20 pin DIP (Commercial) & 20 pin PLCC Packages (Commercial, Extended) s Temperature Ranges, * Commercial 0C to +70C * Extended -40C to +85 C
Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, at www.lsilogic.com. This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic.
Description
The SEEQ 8023A Manchester Code Converter chip provides the Manchester data encoding and decoding functions of the Ethernet Local Area Network physical layer. It interfaces to the SEEQ 8003 and 8005 Ethernet Data Link Controllers or to the Intel 82586 LAN Controller and any standard Ethernet transceiver as defined by IEEE 802.3 and Ethernet Revision 1.
Pin Configuration
DUAL-IN-LINE TOP VIEW (Commercial Temp Only)
MODE 1 MODE 2 LPBK/WDTD Rx+ 1 2 3 4 5 6 7 8 9 10 20 19 18 17 V CC Tx+ Tx- TxD TxC TxEN (TxEN) X1 X2 COLL+ COLL-
Functional Block Diagram
TxEN WATCHDOG TIMER
Rx- (CSN) CSN (COLL) COLL (RxC) RxC RxD VSS
8023A
16 15 14 13 12 11
TxC ENCODER TxD LPBK/ WDTD CSN X1 X2 RxC RxD DECODER MUX XTAL CLOCK CARRIER SENSE TRANSMIT
Tx+ Tx- VCC VSS MODE 1 MODE 2 RECEIVE Rx+ Rx-
PLASTIC LEADED CHIP CARRIER TOP VIEW (Commercial and Extended Temps)
LPBK/WDTD MODE 2 MODE 1 V CC
3
2
1
20
19
COLL
10MHz DETECTOR COLLISION
COLL+ COLL-
Rx+ Rx- (CSN) CSN (COLL) COLL (RxC) RxC 4 5 6 7 8 9
RxD
Tx+
18 Tx- 17 TxD 16 TxC 15 TxEN (TxEN) 14 10
GND
Figure 1. 8023A MCC Manchester Code Converter Block Diagram. MCC is a trademark of SEEQ Technology, Inc. EDLC is a registered trademark of SEEQ Technology, Inc.
X1
11
COLL-
12
COLL+
13
X2
1
MD400022/D
8023A
The SEEQ 8023A MCC is a functionally complete Encoder/Decoder including ECL level balanced driver and receivers, on board oscillator, analog phase locked loop for clock recovery and collision detection circuitry. In addition, the 8023A includes a 25 millisecond watchdog timer, a 4.5 microsecond window generator, and a loopback mode for diagnostic operation. Together with the 8003 or 8005 and a transceiver, the 8023A Manchester Code Converter provides a high performance minimum cost interface for any system to Ethernet. Manchester Encoder and Differential Output Driver The encoder combines clock and data information for the transceiver. In Manchester encoding, the first half of the bit cell contains the complement of the data and the second half contains the true data. Thus, a transition is always guaranteed in the middle of a bit cell. Data encoding and transmission begin with TxEN going active; the first transition is always positive for Tx(-) and negative for Tx(+). In IEEE mode, at the termination of a transmission, TxEN goes inactive and transmit pair approach to zero differential. In Ethernet mode, at the end of the transmission, TxEN goes inactive and the transmit pair stay differentially high. The transmit termination can occur at bit cell center if the last bit is a one or at a bit boundary if the last bit is a zero. To eliminate DC current in the transformer during idle, Tx is brought to 100 mV differential in 600 ns after the last transition (IEEE mode). The back swing voltage is guaranteed to be less than .1 V. Watchdog timer A 25 ms watchdog timer is built on chip. It can be enabled or disabled by the LPBK/WDTD signal. The timer starts counting at the beginning of the transmission. If TxEN goes inactive before the timer expires, the timer is reset and ready for the next transmission. If the timer expires before the transmission ends, transmission is aborted by disabling the differential transmitter. This is done by idling the differential output drivers (differential output voltage becomes zero) and deasserting CSN. Differential Input Circuit (Rx+ and Rx-, COLL+ and COLL-) As shown in Figure 3, the differential input for Rx+ and Rxand COLL+ and COLL- are externally terminated by a pair of 39.2 1% resistors in series for proper impedance matching.
Functional Description
The 8023A Manchester Code Converter chip has two portions, transmitter and receiver. The transmitter uses Manchester encoding to combine the clock and data into a serial stream. It also differentially drives up to 50 meters of twisted pair transmission line. The receiver detects the presence of data and collisions. The 8023A MCC recovers the Manchester encoded data stream and decodes it into clock and data outputs. Manchester Encoding is the process of combining the clock and data stream so that they may be transmitted on a single twisted pair of wires, and the clock and data may be recovered accurately upon reception. Manchester encoding has the unique property of a transition at the center of each bit cell, a positive going transition for a "1", and a negative going transition for a "0" (See Figure 2). The encoding is accomplished by exclusive-ORing the clock and data prior to transmission, and the decoding by deriving the clock from the data with a phase locked loop. Clock Generator The Internal oscillator is controlled by a 20 MHz parallel resonant crystal or by an external clock on X1. The 20 MHz clock is then divided by 2 to generate a 10 MHz 0.01% transmitter clock. Both 10 MHz and 20 MHz clocks are used in Manchester data encoding.
+
1 SERIAL DATA 0 1 1 0 0
COLLISION OR RECEIVE INPUT
39.2 1% TRANSCEIVER CABLE 39.2 1%
0.01 F
TRANSMITTED DATA (MANCHESTER ENCODED)
-
Figure 2. Manchester Coding
Figure 3. Differential Input Terminator
2
MD400022/D
8023A
The center tap has a 0.01 F capacitor, tied to ground, to provide the AC common mode impedance termination for the transceiver cable. Both collision and receiver input circuits provide a static noise margin of -140 mV to -300mV (peak value). Noise rejection filters are provided at both input pairs to prevent spurious signals. For the receiver pair, the range is 15 ns to 30 ns. For the collision pair, the range is 10 ns to 18 ns. The D.C. threshold and noise rejection filter assure that differential receiver data signals less than -140 mV in amplitude or narrower than 15 ns (10 ns for collision pair) are always rejected, signals greater than -300 mV and wider than 30 ns (18 ns for collision pair) are always accepted. Manchester Decoder and Clock Recovery Circuit The filtered data is processed by the data and clock recovery circuit using a phase-locked loop technique. The PLL is designed to lock onto the preamble of the incoming signal with a transition width asymmetry not greater than +8.25 ns to -8.25 ns within 12 bit cell times worst case and can sample the incoming data with a transition width asymmetry of up to +8.25 ns to -8.25 ns. The RxC high or low time will always be greater than 40 ns. If MODE2 is high or floating, RxC will be held low for 1.2 s maximum while the PLL is acquiring lock. If MODE2 is low, RxC follows TxC for the first 1.2 s and then switches to the recovered clock. In addition, the Encoder/Decoder asserts the CSN signal while it is receiving data from the cable to indicate the receiver data and clock are valid and available. At the end of the frame, after the node has finished receiving, CSN is deasserted and will not be asserted again for a period of 4.5 s regardless of the state of the state of the receiver pair or collision pair. This is called the inhibit period. There is no inhibit period after packet reception. During clock switching, RxC may stay high for 200ns maximum. Collision Circuit A collision on the Ethernet cable is sensed by the transceiver. It generates a 10 MHz 15% differential square wave to indicate the presence of the collision. During the collision period, CSN is asserted asynchronously with RxC. However, if a collision arrives during inhibit period 4.5 s from the time CSN was deasserted, CSN will not be reasserted. Loopback In loopback mode, encoded data is switched to the PLL instead of Tx+/Tx- signals. The recovered data and clock are returned to the Ethernet Controller. All the transmit and receive circuits, including noise rejection filter, are tested except the differential output driver and the differential input receiver circuits which are disabled during loopback. At the end of frame transmission, the 8023A also generates a 650 ns long COLL signal 550 ns after CSN was deasserted to simulate the IEEE 802.3 SQE test. The watchdog timer remains enabled in this mode.
Pin Description
The MCC chip signals are grouped into four categories: * * * * Power Supply and Clock Controller Interface Transceiver Interface Miscellaneous
Power Supply VCC ............................................................................+5V VSS .......................................................................Ground X1 and X2 clock (Inputs): Clock Crystal: 20 MHz crystal oscillator input. Alternately, pin X1 may be used at a TTL level input for external timing by floating pin X2.
Controller Interface
RxC (RxC) Receive Clock (Output): This signal is the recovered clock form the phase decoder circuit. It is switched to TxC when no incoming data is present from which a true receive clock is derived. 10 MHz nominal and TTL compatible. If the MODE2 signal is high, RxC is inverted (RxC) and there is a 1.25 sec discontinuity at the beginning of frame reception. RxD Receive Data (Output): The RxD signal is the recovered data from the phase decoder. During idle periods, the RxD pin is LOW under normal conditions. However, if the MODE2 signal is HIGH, the RxD output will be HIGH during idle. TTL and MOS level compatible. Active HIGH. CSN (CSN) Carrier Sense (Output): The Carrier Sense Signal indicates to the controller that there is activity on the coaxial cable. It is asserted when receive data is present or when a collision signal is present. It is deasserted at the end of frame or at the end of collision, whichever occurs later. It is asserted or deasserted synchronously with RxC. TTL compatible. Normally active HIGH, unless MODE2 is HIGH, in which case CSN is active LOW. TxC Transmit Clock (Output): A 10 MHz signal derived from the internal oscillator. This clock is always active. TTL and MOS level compatible. TxD Transmit Data (Input): TxD is the NRZ serial input data to be transmitted. The data is clocked into the MCC by TxC. Active HIGH, TTL compatible.
3
MD400022/D
8023A
TxEN (TxEN ) Transmit Enable (Input): Transmit Enable, when asserted, enables data to be sent to the cable. It is asserted synchronously with TxC. TxEN goes active with the first bit of transmission. TTL compatible. If MODE2 is HIGH, TxEN is inverted. COLL (COLL) Collision (Output): When asserted, indicates to the controller the simultaneous transmission of two or more stations on network cable. TTL Compatible. If MODE2 is HIGH, COLL is inverted. Transceiver Interface Rx+ and Rx- Differential Receiver Input Pair (Input): Differential receiver input pair which brings the encoded receive data to the 8023A. The last transition is always positive-going to indicate the end of the frame. COLL+ and COLL- Differential Collision Input Pair (Input): This is a 10 MHz 15% differential signal from the transceiver indicating collision. The duty cycle should not be worse than 60%/40% - 40%/60%. The last transition is positive-going. This signal will respond to signals in the range of 5 MHz to 11.5 MHz. Collision signal may be asserted if `MAU not available' signal is present. Tx+ and Tx- Differential Transmit Output Pair (Output): Differential transmit pair which sends the encoded data to the transceiver. The cable driver buffers are source follower and require external 243 resistors to ground as loading. These resistors must be rated at 1 watt to withstand the fault conditions specified by IEEE 802.3. If MODE1=1, after 200 ns following the last transition, the differential voltage is slowly reduced to zero volts in 8 s to limit the back swing of the coupling transformer to less than 0.1 V.
Miscellaneous
MODE1 (Input): This pin is used to select between AC or DC coupling. When it is tied high or left floating, the output drivers provide differential zero signal during idle (IEEE 802.3 specification). When pin 1 is tied low, then the output is differentially high when idle (Ethernet Rev.1 specification). MODE2 (Input): The MODE2 Input signal is normally active LOW. In this configuration, the 8032A operates in a mode compatible with the SEEQ 8003. An alternate mode of operation my be achieved by configuring the
1 3 LPBK/WDTD 14 20 MHz XTAL 20 pF 13 20 pF Rx- 8 9 6 7 RxC RxD CSN COLL Tx+ 19 243 1% Tx- 18 1W 10 DO-B AUI CABLE LPBK/ WDTD X1 Rx+ X2 5 39.2 1% 3 4 39.2 1% 12 DI-B 5 DI-A MODE 1 0.01 F
8005 OR 82586
DO-A
16 17 15
SEEQ 8023A
TxC TxD TxEN
243 1% 1W 12 39.2 1% COLL- 11 9 39.2 1% 20 0.01 F +5 CI-B 2
COLL+
CI-A
MODE 2
10
Figure 4. 8023A Interface
4
MD400022/D
8023A
MODE signal active HIGH, or by allowing it to float HIGH with its internal pullup. In this configuration, RxC, TxEN, CSN and COLL become active LOW. In addition, RxD is HIGH during idle, and RxC has 1.2 s discontinuity during signal acquisition. LPBK/WDTD Loopback/Watchdog Timer Disable (Input): Normal Operation: For normal operation this pin should be HIGH or tied to VCC. In normal operation the watchdog timer is enabled. Loopback: When this pin is brought low, the Manchester encoded transmit data from TxD and TxC is routed through the receiver circuit and sent back onto the RxD and RxC Pins. During loopback, Collision and Receive data inputs are ignored. The transmit pair is idled. At the end of transmission, the signal quality error test (SQET) will be simulated by asserting collision during the inhibit window. During loopback, the watchdog timer is enabled. Watchdog Timer Disable: When this pin is between 10 V (Min.) and 16 V (Max.), the on chip 25 ms Watchdog Timer will be disabled. The watchdog timer is used to monitor the transmit enable pin. If TxEN is asserted for longer than 25 ms, then the watchdog timer (if enabled) will automatically deassert CSN and inhibit any further transmissions on the Tx+ and Tx- lines. The watchdog timer is automatically reset each time TxEN is deasserted. Interconnection to a Data Link Controller Figure 5 shows the interconnections between the 8023A MCC and SEEQ's 8003 or 8005. There are three connections for each of the two transmission channels, transmit and receive, plus the Collision Signal line (COLL). Transmitter connections are: Transmit Data, TxD Transmit Clock, TxC Transmit Enable, TxEN Collision, COLL Receiver connections are: Receive Data, RxD Receive Clock, RxC Carrier Sense, CSN Compatibility with Other LAN Controllers SEEQ's 8023A is compatible with other LAN Controllers, such as the 82586, when Pin 2 (MODE2) of the 8023A is floating or tied to VCC. In this mode of operation, timing and polarity on the controller interface lines are compatible, with the 82586 specifications dated March 1984. Use of Time Domain Reflectometry in the 82586 is not recommended since the TDR transmission does not have a valid preamble.
D.C. and A.C. Characteristics and Timing
Crystal Specification
Resonant Frequency (CL = 20 pF) ..................... 20 MHz 0.005% 0-70 C and 0.003% at 25 C Type ................................................. Fundamental Mode Circuit .............................................. Parallel Resonance Load Capacitance (CL ) ........................................... 20pF Shunt Capacitance (CO ) .................................. 7pF Max. Equivalent Series Resistance (R1) ................. 25 Max. Motional Capacitance (C1) ........................ 0.02 pF Max. Drive Level ............................................................. 2mW
TxD TxC TxEN LOOPBACK [1] 8003 OR 8005 COLL RxD RxC CSN
TxD TxC TxEN LOOPBACK 8023A MCC COLL RxD RxC CSN MODE 2
R1
C1
L1
C0 EQUIVALENT CIRCUIT OF CRYSTAL
Figure 5. Interconnection of 8023A and 8003/8005
NOTE 1. Loopback output on 8005 only.
Figure 6.
5
MD400022/D
8023A
Absolute Maximum Range*
Storage Temperature ......................... -65C to +150C All Input or Output Voltage .................. - 0.3 to VCC +0.3 VCC.... .............................................................. -0.3 to 7V (Rx, Tx, COLL ) High Voltage Short Circuit Immunity .............................. -0.3 to 16V *COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
Symbol IIL Parameter
TA = Commercial 0C to +70C, TC = Extended -40C to +85C; VCC = 5 V 5% Min. Max. 10 Unit A Conditions 0 VIN VCC
Input Leakage Current (except MODE1, MODE2 Receive and Collision Pairs) MODE1Input Leakage Current Receive and Collision Pairs(Rx, COLL) Input Leakage Current
200 2 75 -0.3 2.0 3.5 0.8 VCC + 0.3 VCC + 0.3 0.4 0.4 2.4 3.9 0.55 VCC -2.5 1.2 VCC-1 0.1 0.3 0 1.2 VCC 15 15
A mA mA V V V V V V V V V V V V pF pF
0 VIN VCC VIN = 0 All Inputs, Outputs Open
ICC VIL VIH VOL
VCC Current TTL Input Low Voltage TTL Input High Voltage (except X1) X1 Input High Voltage TTL Output Low Voltage except TxC TxC Output Low Voltage
IOL = 2.1 mA IOL = 4.2 mA tOH = -400 A tOH = -400 A 78 Termination Resistor and 243 Load Resistors 78 Termination Resistor and 243 Load Resistors Shunt Inductive Load 27 H
VOH
TTL Output High Voltage (except RxC, TxC, RxD) RxC, TxC, RxD Output High Voltage
VODF VOCM VBKSV VIDF VICM CIN[1] COUT[1]
NOTE:
Differential Output Swing Common Mode Output Voltage Tx Backswing Voltage During Idle Input Differential Voltage (measured differentially) Input Common Mode Voltage Input Capacitance Output Capacitance
1. Characterized. Not tested
6
MD400022/D
8023A
A.C. Test Conditions
Output Loading TTL Output: Differential Output: 1 TTL gate and 20 pF capacitor. 243 resistor and 10 pF capacitor from each pin to VSS and a termination 78 resistor load resistor in parallel with a 27 H inductor between the two differential output pins 50% point of swing 20% to 80% points High time measured at 3.0V Low time measured at 0.6V Measured between 0.6V and 3.0 V points 0.8V to 2.0V with 10 ns rise and fall time 0.8V to 3.5V with 5 ns rise and fall time At least 300 mV with rise and fall time of 10 ns measured between -0.2V and +0.2V
Differential Signal Delay Time Reference Level: Differential Output Rise and Fall Time: RxC, TxC, X1 High and Low Time:
RxD, RxC, TxC, X1 Rise and Fall Time: TTL Input Voltage (except X1): X1 Input Voltage: Differential Input Voltage:
20 MHz TTL Clock Input Timing
TA = Commercial 0C to +70C, TC = Extended -40C to +85C; VCC = 5 V 5% Symbol t1 t2 t3 t4 t5 t5A Parameter X1 Cycle Time X1 High Time X1 Low Time X1 Rise Time X1 Fall Time X1 to TxC Delay Time 10 Min. 49.995 15 15 5 5 45 Max. 50.005 Unit ns ns ns ns ns ns
t2 X1 t1
t4
t5
t3
TxC t 5A t 5A
Figure 12. 20 MHz TTL Clock Timing
7
MD400022/D
8023A
Transmit Timing
Symbol t6[1] t7 t8 t9[1] t10[1] t11 TA = Commercial 0C to +70C, TC = Extended -40C to +85C; VCC = 5 V 5% Min. 99.99 40 40 5 5 40 55 40 55 99.5 49.5 100.5 50.5 5 5 200 400 600 Max. 100.01 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter TxC Cycle Time TxC High Time TxC Low Time TxC Rise Time TxC Fall Time TxEN Setup Time if Mode 2=0 TxEN Setup Time if Mode 2=1
t12
TxD Setup Time if Mode 2=0 TxD Setup Time if Mode 2=1
t13[1] t14[1] t15[1] t16[1] t17 t17A[1]
Bit Center to Bit Center Time Bit Center to Bit Boundary Time Tx+ and Tx - Rise Time Tx+ and Tx - Fall Time Transmit Active Time From The Last Positive Transition From Last Positive Transition of the Transmit Pair to Differential Output Approaches within 100 mV of 0 V From Last Positive Transition of the Transmit Pair to Differential Output Approaches within 40 mV of 0 V Tx+ and Tx- Output Delay Time TxD Hold Time if Mode 2=0 TxD Hold Time if Mode 2=1 TxEN Hold Time if Mode 2=0 TxEN Hold Time if Mode 2=1
t17B[1]
7000
ns
t18 t19 t20
70 15 0 15 0
ns ns ns ns ns
NOTE: 1. Characterized. Not tested.
8
MD400022/D
8023A
MODE1 = 1 MODE2 = 0 t6 TxC t 11 TxEN [1] t 19 t 12 TxD "1" "0" "1" "1" LAST BIT"0/1" t 17B t 17A t 17 t 18 Tx LAST BIT 0 (-) (+) 1 | 0 t 13 (-) (+) 1 | 1 | 0 | (-) t 17B t 17A t 17 t 16 Tx LAST BIT 1 (-) (+) 1 | 0 1 | 0 | 1 | (-) (+) t 14 t 15 (+) t8 t 20 t 11 t7 t 10 t9
Figure 7. Transmit Timing
MODE1 = 0 MODE2 = 0 t6 TxC t 11 TxEN [1] t 19 t 12 TxD t 18 Tx (+) LAST BIT = 0 Tx (-) (-) (+) 1 | 0 "1" "0" t 13 (-) (+) 1 | 1 t 16 Tx (+) LAST BIT = 1 Tx (-) | (-) (+) 1 | 0 1 | 1 | 1 | (-) | 0 (-) "1" "1" LAST BIT"0/1" t 14 t 15 t8 t 20 t 11 t7 t 10 t9
Figure 8. Transmit Timing
NOTE: 1. If MODE 2=1, TxEN becomes active low signal TxEN.
9
MD400022/D
8023A
Receive Timing
Symbol t21 t22 t23A t23B t24 t25A t25B t26[1] t
[1] 27
TA = Commercial 0C to +70C, TC = Extended -40C to +85C; VCC = 5 V 5% Min. Max. 240 240 Unit ns ns
Parameter CSN Assert Delay Time CSN Deasserts Delay Time (measured from Last Bit Boundary) CSN Hold Time CSN Set up Time CSN Deassertion Delay Time RxD Hold Time RxD Set up Time RxC, RxC Rise and Fall Time During Clock Switch RxC Keeps High, RxC Keeps Low Time
30 30 10 30 30 5 40 200 35
ns ns ns ns ns ns ns
t28 t29[1] t30 t31 t
[1] 32
RxC, RxC High and Low Time RxC, RxC Clock Cycle Time (during) Data Period CSN Inhibit Time (on Transmission Node only) Rx+/Rx- Rise and Fall Time RxC Held Low Duration from First Valid Negative-Going Transition RxC Stops Delay Time from First Valid Negative-Going Transition Rx+/Rx- Begin Return to Zero from Last Positive-Going Transition
40 95 4.3 105 4.6
ns ns s
10 1.15 1.35 240 160
ns s ns ns
t33 t34[1] t35[1] t36[1]
RxD Rise Time RxD Fall Time
10 10
ns ns
NOTE: 1. Characterized. Not tested.
10
MD400022/D
8023A
Rx(+) Rx(-) MODE 2 = 0 CSN t 23A RxC t 23B RxD t 21 MODE 2 = 1 CSN t 32 RxC t 33 RxD t 25A t 25B t 36 t 25B RxC FOLLOWS TxC t 28 t 25A t 35 t 26 t 27 t 26 t 28 (-) (+) t 21 t 31 t 31 (-) (+) (+) (-)
Figure 9. Receive Timing-Start of Packet
MODE 2 = 0 t 27
RxC t 29 Rx(+) Rx(-) (LAST BIT = 0) CSN t 22 RxD "1" "0" t 30 (-) (+) (+) (-) t 23A t 23B t 29
MODE 2 = 1
t 29
RxC t 34 Rx(+) Rx(-) (LAST BIT = 1) CSN t 30 (-) (+) (+) (-) t 24 t 27
"1" RxD
|
"1"
|
Figure 10. Receive Timing -- End of Packet
11
MD400022/D
8023A
Collision Timing
Symbol t51 t52 t53 t54 t55 t56 t57 t58 TA = Commercial 0C to +70C, TC = Extended -40C to +85C; VCC 5 V 5% Min. 86 Max. 118 10 35 26 300 500 400 600 70 Unit ns ns ns ns ns ns ns ns
Parameter COLL+ /COLL -- Cycle Time COLL+/COLL -- Rise and Fall Time COLL+/COLL -- High and Low Time COLL+/COLL -- Width (measured at -0.3 V) COLL Asserts Delay Time COLL Deasserts Delay Time CSN Asserts Dealy Time CSN Deasserts Delay Time
NOTES: 1. COLL + and COLL - asserts and deasserts COLL, asynchronously, and asserts and deasserts CSN synchronously with RxC. 2. If COLL + and COLL - arrives within 4.5s from the time CSN was deasserted; CSN will not be reasserted (on transmission node only). 3. When COLL + and COLL - terminates, CSN will not be deasserted if Rx+ and Rx- are still active. 4. When the node finishes transmitting and CSN is deasserted, it cannot be asserted again for 4.5 s. 5. If MODE 2=1, then COLL and CSN are inverted.
MODE 2=0 t 53 COLL(+) COLL(-) (-) (+) t 54 t 55 COLL
t 51
t 52 (-) (+) t 56
t 57 CSN
t 58
Figure 11. Collision Timing
12
MD400022/D
8023A
Loopback Timing
Symbol t61 t62 t63 t64 TA = Commercial 0C to +70C, TC = Extended -40C to +85C; VCC = 5 V 5% Min. 500 5 475 625 Max. Unit ns s ns
Parameter LPBK Setup Time LPBK Hold TIme In Collision Simulation, COLL Signal Delay Time COLL Duration Time
600
750
ns
NOTES: 1. PLL needs 12-bit cell times to aquire lock, RxD is invalid during this period. RxC is low for 1.35 s (max) if MODE2 = 1. RxD = 0 if MODE2 = 0. RxD = 1 if MODE2 = 1.
MODE 2=0
LPBK/WDTD
TxC t 61 TxEN t 62
| TxD
"1"
|
"0"
|
"1"
|
"0"
|
"0"
|
"1"
|
|
"1"
|
(LAST BIT)
COLL (NOTE 1) RxC t 63 CSN t 64
| RxC
"1"
|
"0"
|
"1"
|
|
"1"
|
Figure 12. Loopback Timing
13
MD400022/D
8023A
MODE2 = 1
LPBK/WDTD
TxC t 61 TxEN t 62
| TxD
"1"
|
"0"
|
"1"
|
"0"
|
"0"
|
"1"
|
|
"1"
|
(LAST BIT) t 63 t 64
COLL
RxC
(NOTE 1)
CSN
| RxD
"1"
|
"0"
|
"1"
|
|
"1"
|
Figure 13. Loopback Timing --(Cont.)
14
MD400022/D
8023A
Ordering Information
NE 8023A
PACKAGE TYPE N = PLCC
TEMPERATURE RANGE E= -40C to +85C EXTENDED TEMPERATURE Q = 0C to +70C COMMERCIAL TEMPERATURE
PART TYPE 8023A = MCC MANCHESTER CODE CONVERTER
15
MD400022/D

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